Project leader
Laboratoire Hubert Curien, Université de Saint EtiennePartners
NETHEOS, Telecom ParisTech, LIRMM, LAB STICFunders
ANR,![](https://www.pole-scs.org/wp-content/themes/polescs/assets/images/projet-innovant.png)
SECRESOC
The goal of this project is to develop a multiprocessor architecture allowing the integration into an FPGA target (standard or specific) of an application requiring different levels of data security.